Modern semiconductor based integrated circuits (ICs) are incredibly complex and contain millions of circuit devices, such as transistors, and millions of interconnections between the circuit devices. Designing such complex circuits cannot be accomplished manually, and circuit designers use computer based Electronic Design Automation (EDA) tools for schematics, layouts, simulation, and verification of the complex circuits. A significant step of designing and validating a complex IC is power verification and signoff. For example, an EDA tool should verify that components within the IC receive and consume power within respective constraints, that the overall power flow within the IC is optimized, and that IC is able to handle catastrophic power conditions wherein the IC experiences a transient or prolonged power overload.
An example of catastrophic power condition is electrostatic discharge (abbreviated as ESD), which is a very common cause of IC failures. An ESD is a sudden flow of electric current, often a high current, between two electrically charged objects. For example, ESD events produce high currents into the input pins of an IC chip. Such high current in the IC chip may cause functional failure and in many cases may cause an oxide damage resulting in a complete circuit breakdown. To mitigate circuit damage from an ESD event, circuit designers insert protection circuits within the IC. A protection circuit design may comprise ESD cells. An ESD cell may clamp high voltage and drain a high current through a safe discharge path such as a ground pin. The ESD cells within an IC design have to be tested during power verification and signoff stage of the IC design.
Conventional systems and methods of testing ESD cells have several technical shortcomings. For example, in a conventional system, circuit designers have to manually setup a test bench specific to an IC design being tested. If another IC design has to be tested, the circuit designers have to setup another test bench. This approach is cumbersome, time-consuming, and prone to errors. Furthermore, ESD events generated by manual test benches may not be accurate and may generate invalid test results.